Synthesis of Anti-Aging Gated Clock Designs

As device dimensions shrink to deep sub-micron ranges, the hot-carrier effect is a main concern for the long-term reliability. It is known that the delay degradation (induced by the hot-carrier effect) of a logic gate is linearly proportional to the number of output switching activities. Due to the clock gating design, the clock gates often have different active probabilities, which lead to different delay degradations. The difference among the delay degradations of clock paths results in an additional clock skew, called aging skew. Based on that observation, in this paper, we present the first attempt, called anti-aging clock gating (AACG), for the synthesis of gated clock designs with the aging skew considered. Given a constraint on the power consumption, the objective of our AACG is to minimize the aging skew (by equalizing the delay degradations of clock paths as possible). Two integer linear programs (ILP) are proposed to formally draw up our AACG problem in the register-transfer-level (RTL) synthesis stage and the high-level synthesis stage, respectively. Compared with previous works, benchmark data show that our approach can greatly reduce the aging skew without any penalty on the power consumption.